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INTEGRATED CIRCUITS
74F564 Octal D flip-flop (3-State)
Product specification IC15 Data Handbook 1996 Jan 05
Philips Semiconductors
Philips Semiconductors
Product specification
Octal D flip-flop (3-State)
74F564
FEATURES
* 74F564 is broadside pinout version of 74F534 * Inputs and Outputs on opposite side of package allow easy
interface to Microprocessors
PIN CONFIGURATION
OE 1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CP
* Useful as an Input or Ouput port for Microprocessors * 3-State Ouputs for Bus interfacing * Common Output Enable * 74F574 is a non-inverting version of 74F564
DESCRIPTION
The 74F564 has a broadside pinout configuration to facilitate PC board layout and allows easy interface with microprocessors. It is an 8-bit, edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE) control gates. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (OE) controls all eight 3-State buffers independently of the register operation. When OE is Low, data in the register appears at the outputs. When OE is High, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus.
GND 10
SF01052
TYPE 74F564
TYPICAL fMAX 180MHz
TYPICAL SUPPLY CURRENT (TOTAL) 50mA
ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic DIP 20-Pin Plastic SOL COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F564N N74F564D PKG. DWG # SOT146-1 SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS D0 - D7 OE CP Data inputs Output Enable input (active Low) Clock Pulse input (active rising edge) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 150/40 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/0.6mA 3.0mA/24mA
Q0 - Q7 3-State outputs NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20A in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
2 3 4 5 6 7 8 9
LOGIC SYMBOL (IEEE/IEC)
1 11 C2 D1 D2 D3 D4 D5 D6 D7 EN1
D0 11 CP
2 3 4
2D
1
19 18 17 16 15 14 13 12
1
OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
5 6 7 19 18 17 16 15 14 13 12 8 9
VCC=Pin 20 GND=Pin 10
SF01053
SF01054
1996 Jan 05
2
853-0166 16189
Philips Semiconductors
Product specification
Octal D flip-flop (3-State)
74F564
LOGIC DIAGRAM
D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
CP
11
OE
1 19 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7
VCC=Pin 20 GND=Pin 10
Q0
SF01055
FUNCTION TABLE
INPUTS OE L L L H H H= h= L= l= NC= X= Z= = = CP Dn l h X X Dn INTERNAL REGISTER L H NC NC Dn OUTPUTS Q0 - Q7 H L NC Z Z OPERATING MODES Load and read register Hold Disable outputs
High voltage level High voltage level one setup time prior to the Low-to-High clock transition Low voltage level Low voltage level one setup time prior to the Low-to-High clock transition No change Don't care High impedance "off" state Low-to-High clock transition Not a Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5.0 -0.5 to +VCC 48 0 to +70 -65 to +150 UNIT V V mA V mA C C
1996 Jan 05
3
Philips Semiconductors
Product specification
Octal D flip-flop (3-State)
74F564
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER LIMITS MIN 4.5 2.0 0.8 -18 -3 24 70 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) LIMITS SYMBOL PARAMETER TEST CONDITIONSNO TAG 10%VCC 5%VCC 10%VCC 5%VCC MIN 2.4 2.7 3.4 0.35 0.35 -0.73 0.50 0.50 -1.2 100 20 -0.6 50 -50 -60 45 VCC = MAX 50 -150 65 75 TYP
NO TAG
MAX
UNIT V V V V V A A mA A A mA mA mA
VO OH
High-level High level output voltage
VCC = MIN, VIL = MAX, VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX
VO OL VIK II IIH IIL IOZH IOZL IOS ICC
Low-level Low level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Off-state output current, High-level voltage applied Off-state output current, Low-level voltage applied Short-circuit output currentNO TAG ICCH Supply current (total) ICCL
ICCZ 55 80 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
1996 Jan 05
4
Philips Semiconductors
Product specification
Octal D flip-flop (3-State)
74F564
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb= +25C VCC = +5V CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Clock frequency Propagation delay CP to Qn Output Enable time to High or Low level Output Disable time from High or Low level Waveform NO TAG Waveform NO TAG Waveform 4 Waveform 5 Waveform 4 Waveform 5 160 3.5 3.5 2.5 4.0 1.0 1.0 TYP 180 5.0 5.0 4.5 5.5 3.0 2.5 8.0 8.0 7.5 8.0 6.0 5.5 MAX Tamb = 0C to +70C VCC = +5V 10% CL = 50pF, RL = 500 MIN 150 3.0 3.0 2.0 3.5 1.0 1.0 8.5 8.5 8.0 8.5 7.0 6.0 MAX MHz ns ns ns UNIT
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb= +25C VCC = +5V CL = 50pF, RL = 500 MIN ts(H) ts(L) th(H) th(L) tw(H) tw(L) Setup time, Dn to CP Hold time, Dn to CP CP pulse width, High or Low Waveform 3 Waveform 3 Waveform NO TAG 2.0 2.0 1.0 1.0 3.5 3.5 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 2.0 2.5 1.5 1.5 3.5 3.5 MAX ns ns ns UNIT
AC WAVEFORMS
For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fMAX Dn CP VM tW(H) tPHL Qn VM VM tW(L) tPLH VM Qn VM VM VM VM tPHL VM tPLH
SF01051
SF00990
Waveform 1. Propagation Delay, Clock and Enable Inputs to Output, Enable, Clock Pulse Widths, and Maximum Clock Frequency
Waveform 2. Propagation Delay for Data to Outputs
1996 Jan 05
5
Philips Semiconductors
Product specification
Octal D flip-flop (3-State)
74F564
AC WAVEFORMS (Continued)
For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance.
Dn
VM
VM
VM
VM
OE
VM tPZH
VM tPHZ VM 0V VOH -0.3V
ts(H)
th(H)
ts(L)
th(L) Qn
CP
VM
VM
SF00993
SF00994
Waveform 3. Data Setup and Hold Times
Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level
OE
VM tPZL
VM tPLZ VM VOL +0.3V
Qn
SF00995
Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORM
VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V)
90%
Test Circuit for 3-State Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open
VM
Input Pulse Definition
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00777
1996 Jan 05
6
Philips Semiconductors
Product specification
Octal D flip-flop (3-State)
74F564
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
1996 Jan 05
7
Philips Semiconductors
Product specification
Octal D flip-flop (3-State)
74F564
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1996 Jan 05
8
Philips Semiconductors
Product specification
Octal D flip-flop (3-State)
74F564
NOTES
1996 Jan 05
9
Philips Semiconductors
Product specification
Octal D flip-flop (3-State)
74F564
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. (c) Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. (print code) Document order number: Date of release: July 1994 9397-750-05138

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